This invention relates to a light-emitting diode and a method for manufacturing same, an integrated light-emitting diode and a method for making same, a method for growing a nitride-based III-V Group compound semiconductor, a substrate for growing a nitride-based III-V Group compound semiconductor, a light source cell unit, a light-emitting diode backlight, a light-emitting diode illuminating device, a light emitting diode display, an electronic instrument, and an electronic device and a method for manufacturing same. The invention is suited for application, for example, to a light-emitting diode using a nitride-based III-V Group compound semiconductor and also to various types of instruments or devices using the light-emitting diode.
In case where a GaN semiconductor is epitaxially grown on a hetero-substrate such as a sapphire substrate, crystal defects, especially, threading dislocations, occur in high density owing to the great difference in lattice constant or coefficient of thermal expansion therebetween.
To avoid this problem, a dislocation density reducing technique based on selective lateral growth has been hitherto in wide use. In this technique, a GaN semiconductor is epitaxially grown on a sapphire substrate or the like, after which the substrate is removed from a crystal growth device. A growth mask made of a SiO2 film or the like is formed on the GaN semiconductor layer, and the substrate is returned to the crystal growth device, followed by epitaxially growing a GaN semiconductor once more by use of the growth mask.
According to this technique, although the dislocation density in the upper GaN semiconductor layer can be reduced, the epitaxial growth is needed twice, resulting in high costs.
To cope with this, there has been proposed a method, in which a hetero-substrate is subjected to patterned indentation and a GaN semiconductor is epitaxially grown on the indented substrate (e.g. see Mitsubishi Cable Industries Review No. 98, October, 2001, entitled “Development of High Output UV LED Using an LEPS Technique” and Japanese Patent Laid-open Nos. 2004-6931 and 2004-6937). The outline of this method is shown in FIGS. 77A to 77C. According to this method, as shown in FIG. 77A, patterned indentation is made in one main surface of the c face of a sapphire substrate 101. A recessed portion is indicated by reference numeral 101a and a protruded portion is indicated by reference numeral 101b. These recessed portions 101a and protruded portions 101b, respectively, extend along a <1-100> direction of the sapphire substrate 101. Next, a GaN semiconductor layer 102 is formed over the sapphire substrate 101 via the steps shown in FIGS. 77B and 77C. In FIG. 77C, the dotted line indicates a growth interface in the course of the growth. As is particularly shown in FIG. 77C, it is characteristically observed that the recessed portion 101a is unfavorably formed with a space 103 between the sapphire substrate 101 and the GaN semiconductor 102. The distribution of crystal defects in the GaN semiconductor layer 102 grown by the method is schematically shown in FIG. 78. As shown in FIG. 78, threading dislocations 104 occur at a portion over the protruded portion 101b of the GaN semiconductor layer 102 in a direction vertical to the interface with an upper surface of the protruded portion 101b, thereby forming a high defect density region 105. On the other hand, an area or portion above the recessed portion 101a becomes a low defect density region 106 at a portion between the high defect density regions 105.
It will be noted that although, in FIG. 77C, the GaN semiconductor layer 102 beneath the space 103 formed within the recessed portion 101a of the sapphire substrate 101 is buried in the form of a rectangle, the buried form may be triangular in some case. In the latter case, the GaN semiconductor layer 102 buried inside the recessed portion 101a is in contact with the GaN semiconductor layer 102 laterally grown from the protruded portion 101b, with the possibility that a space is formed, like the rectangular form.
For reference, there is shown in FIGS. 79A to 79D how a GaN semiconductor layer 102 is grown in case where the direction of extension of the recessed portions 101a and the protruded portions 101b is a <11-20> direction of intersecting at right angles with a <1-100> direction of the sapphire substrate 101.
FIGS. 80A to 80F schematically show another conventional growth method (Refer to, for example, Japanese Patent Laid-open No. 2003-31441). In this method, as shown in FIG. 80A, a sapphire substrate 101 subjected to patterned indentation is used, and a GaN semiconductor layer 102 is grown thereon through the steps shown in FIGS. 80B to 80F. It is stated that according to the method, the GaN semiconductor layer 102 can be grown without formation of a space in relation with the sapphire substrate 101.
A further growth method has been proposed in which protruded portions are formed on a substrate using a material different from that of the substrate and a nitride III-V Group compound semiconductor starts to be grown from a recess portion between the protruded portions (see, for example, Japanese patent Laid-open No. 2003-324069 and Japanese Patent No. 2830814). However, the manner of the growth in this method greatly differs from that of the present invention.
Only for reference, main crystal faces and crystal orientations of sapphire are shown in FIGS. 81A and 81B.